In the read and refresh operation cycles of a DRAM, the charge on a memory cell capacitor, representing one bit (binary digit) of the memory which may be "0" or "1", is effectively compared with the charge on a reference
cell capacitor to determine whether the bit is "0" or "1". For the best signal margin, i.e. discrimination between the "0" and "1" charge states, the reference cell capacitor is desirably charged to a midpoint voltage which is mid-way between the voltages of the memory cell capacitor representing the "0" and "1" bits. After each read or refresh operation, the charge on the reference cell capacitor must be restored. Normally, the voltages corresponding to the "0" and "1" are a ground potential (0 volts) and a supply voltage (e.g. 5.0 volts), respectively. Thus, the midpoint voltage is a half of the supply voltage.
A reference voltage generator, which can provide such a midpoint reference voltage to bit lines of a DRAM, is disclosed, for example, in FIG. 3 of an article by Peter Gillingham, Richard C. Foss, Valerie Lines, Gregg Shimokura, and Tomasz Wojcicki. "High-Speed, High-Reliability Circuit Design for Megabit DRAM", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 8, AUGUST 1991, pp. 1171-1175. As shown in FIG. 1 illustrating the prior art herein, that circuit comprises a high impedance bias network stage of a P-channel type FET 11, an N-channel type FET 13, a P-channel type FET 15 and an N-channel type FET 17, which are connected in series between a voltage supply terminal and a ground terminal, or a common potential terminal (0 volt level). The circuit also comprises a complementary source follower output stage of N- and P-channel type FETs 19 and 21, connected in series between io the voltage supply terminal and the ground terminal. The gates of the FETs 19 and 21 are connected to the gates and drains of the FETs 13 and 15, respectively. The bodies of the P-channel FETs 11, 15 and 21 are connected to the sources thereof. A juncture of the sources of both FETs 13 and 15 is referred to as a "node A". A juncture of the sources of both FETs 19 and 21 is referred to as a "node B". The node B is connected to a reference voltage output terminal from which a reference voltage VREF is provided to bit lines of a DRAM (not shown). A juncture of the gates of both FETs 13 and 19 is referred to as a "node C". In addition, a juncture of the gates of both FETs 15 and 21 is referred to as a "node D".
A DC voltage VDD (typically 5.0 volts) is fed to the voltage supply terminal and a current (e.g. 250 .ANG.) flows in the high impedance bias network stage. The FETs 11 and 17 function as resistance elements. A midpoint voltage of VDD/2 (=2.5 volts) is provided at node A. Typical potentials at node A-D are shown in Table I with and without the connection 21A between the body and source of the FET 21.
TABLE I ______________________________________ Potentials (volts) Node with connection 21A without connection 21A ______________________________________ VDD 5.0 5.0 A 2.5 2.5 B 2.5 (2.5-2.8) C 3.5 3.5 D 1.8 1.8 ______________________________________
With the connection 21A, the gate-source bias voltages of the FETs 19 and 21 respectively are the same as those of the FETs 13 and 15, and the reference voltage VREF at node B is the midpoint voltage, which is fed to the DRAM. When the supply voltage VDD changes, the reference voltage VREF has to change to a new midpoint voltage, in order for the DRAM to correctly operate. Also, when the reference voltage VREF changes due to an alteration of the load condition of the DRAM, the reference voltage VREF has to be corrected to the midpoint voltage. Accordingly, the reference voltage generator has to be able to rapidly respond to such voltage changes. Since an input capacitor of the DRAM is large (e.g. in the order of 100 pF), a large current must flow in the FET 19 or 21, to minimize the correction time of the reference voltage VREF. Also, under balanced conditions, a large current (e.g. 10 mA) continues to flow in the FETs 19 and 21. In order for the reference voltage generator to provide an adequate transient response to the output voltage changes, the physical widths of the FETs 19 and 21 must be large, resulting in a large quiescent power consumption. Typical example dimensions of the width W(.mu.m) of the FET channel and the distance L(.mu.m) between the source and the drain thereof are as follows:
FET 11: 10 and 3 PA0 FET 13: 100 and 3 PA0 FET 15: 200 and 3 PA0 FET 17: 3.2 and 3 PA0 FET 19: 2000 and 1.2 PA0 FET 21: 4000 and 1.2
A reduction in the current flowing in the complementary source follower output stage and the FETs' sizes, can be achieved by removing the connection 21A between the body and the source of the FET 21. It results in an increase in the threshold voltage of the FET 21. As the reference voltage VREF at node B approaches that at node A, little current flows in the FETs 19 and 21, resulting in a high impedance at node B.
When the supply voltage VDD changes or when the reference voltage VREF changes due to a change in the load condition of the DRAM, the reference voltage VREF has to be corrected to the midpoint voltage. For example, when the reference voltage VREF changes from 2.5 to 2.7 volts, the gate-source bias voltages of the FETs 19 and 21 are 0.9 volts. Due to the increased threshold voltage, neither FET 19 nor FET 21 is turned on, so that neither FET 19 nor FET 21 correct the reference voltage VREF. As shown in Table I, there is a .dead zone of about 0.3 volts (e.g. 2.5-2.18 volts) in which the FET 19 or 21 cannot pull up or down the changed reference voltage. Therefore, the voltage at node B tends to drift about the midpoint voltage of the dead zone.
As described, the prior art reference voltage generator has disadvantages--either the necessity for a large chip area for the FETs of the complementary source follower output stage in the device forming the reference voltage generator resulting in high power consumption, or poor transient speed in response to a voltage change.